Difference between revisions of "Benchmarking: Coremark"

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| colspan="8"|''MIPS''
 
| colspan="8"|''MIPS''
 
|-
 
|-
−
! scope="row" | Cavium Octeon II CN6645 || 2.50GHz || 10 || 25671 || 10.268 || 2567 || || 10 Threads ||  
+
! scope="row" | Cavium Octeon II CN6645 || 2.50GHz || 10 || 25671 || 10.268 || 2567 || 1.0268 || 10 Threads ||  
 
|-
 
|-
−
! scope="row" | Cavium Octeon II CN6645 || 2.50GHz || 10 || 31172 || 12.468 || 3117 || || 10 Threads || -O3 -funroll-all-loops --param max-inline-insns-auto=200
+
! scope="row" | Cavium Octeon II CN6645 || 2.50GHz || 10 || 31172 || 12.468 || 3117 || 1.2468 || 10 Threads || -O3 -funroll-all-loops --param max-inline-insns-auto=200
 
|-
 
|-
 
| colspan="8"|''ARM''
 
| colspan="8"|''ARM''
 
|-
 
|-
−
! scope="row" | Calxeda Highbank (Cortex A9) || 1.40GHz || 4 || 11764|| 8.403 || 2941 || || 4 Threads ||  
+
! scope="row" | Calxeda Highbank (Cortex A9) || 1.40GHz || 4 || 11764|| 8.403 || 2941 || 2.1007 || 4 Threads ||  
 
|-
 
|-
−
! scope="row" | Calxeda Highbank (Cortex A9) || 1.40GHz || 4 || 12074|| 8.624 || 3018 || || 4 Threads || -O3
+
! scope="row" | Calxeda Highbank (Cortex A9) || 1.40GHz || 4 || 12074|| 8.624 || 3018 || 2.1557 || 4 Threads || -O3
 
|-
 
|-
−
! scope="row" | Calxeda Midway (Cortex A15) || 1.50GHz || 4 || 20284 || 13.523 || 5071 || || 4 Threads ||  
+
! scope="row" | Calxeda Midway (Cortex A15) || 1.50GHz || 4 || 20284 || 13.523 || 5071 || 3.3807 || 4 Threads ||  
 
|-
 
|-
−
! scope="row" | Calxeda Midway (Cortex A15) || 1.50GHz || 4 || 22013 || 14.675|| 5503 || || 4 Threads || -O3
+
! scope="row" | Calxeda Midway (Cortex A15) || 1.50GHz || 4 || 22013 || 14.675|| 5503 || 3.6687 || 4 Threads || -O3
 
|-
 
|-
−
! scope="row" | APM XGene1 (Cortex A57) || 2.40GHz || 8 || 49304 || 20.543 || 6163 || || 8 Threads ||  
+
! scope="row" | APM XGene1 (Cortex A57) || 2.40GHz || 8 || 49304 || 20.543 || 6163 || 2.5679 || 8 Threads ||  
 
|-
 
|-
−
! scope="row" | APM XGene1 (Cortex A57) || 2.40GHz || 8 || 54408|| 22.670 || 6801 || || 8 Threads || -O3
+
! scope="row" | APM XGene1 (Cortex A57) || 2.40GHz || 8 || 54408|| 22.670 || 6801 || 2.8338 || 8 Threads || -O3
 
|-
 
|-
 
| colspan="8"|''Intel''
 
| colspan="8"|''Intel''
 
|-
 
|-
−
! scope="row" | Intel Atom C2550 || 2.4GHz || 4 || 26044 || 10.852 || 6511 || || 4 Threads ||  
+
! scope="row" | Intel Atom C2550 || 2.4GHz || 4 || 26044 || 10.852 || 6511 || 2.7129 || 4 Threads ||  
 
|-
 
|-
−
! scope="row" | Intel Atom C2550 || 2.4GHz || 4 || 29333 || 12.222|| 7333 || || 4 Threads || -O3
+
! scope="row" | Intel Atom C2550 || 2.4GHz || 4 || 29333 || 12.222|| 7333 || 3.0554 || 4 Threads || -O3
 
|-
 
|-
−
! scope="row" | Intel Atom C2750 || 2.4GHz || 8 || 50873 || 21.197 || 6359 || || 8 Threads ||  
+
! scope="row" | Intel Atom C2750 || 2.4GHz || 8 || 50873 || 21.197 || 6359 || 2.6496 || 8 Threads ||  
 
|-
 
|-
−
! scope="row" | Intel Atom C2750 || 2.4GHz || 8 || 58506 || 24.378 || 7313 || || 8 Threads || -O3
+
! scope="row" | Intel Atom C2750 || 2.4GHz || 8 || 58506 || 24.378 || 7313 || 3.0471 || 8 Threads || -O3
 
|-
 
|-
 
|}
 
|}

Revision as of 17:04, 1 April 2014

Decompress

root@jph1:~# tar zxvf coremark_v1.0
cd coremark_v1.0

Adjust compilation flags

Seems to be in ./linux64/core_portme.mak

  • Change PORT_CFLAGS value to -O3
  • Add extra flags to the end of the CFLAGS statement

For example (added -funroll-all-loops --param max-inline-insns-auto=200): 

CC = gcc
# Flag: CFLAGS
#       Use this flag to define compiler options. Note, you can add compiler options from the command line using XCFLAGS="other flags"
PORT_CFLAGS = -O3
FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" -funroll-all-loops --param max-inline-insns-auto=200

Run benchmark (single thread)

Run benchmark with make: 

root@jph1:~/coremark_v1.0# pwd
/root/coremark_v1.0
root@jph1:~/coremark_v1.0# make

Faster systems

If you have a fast system (faster than a RaspberryPi), increase the number of iterations to increase the test run to give a more meaningful result: 

root@jph1:~/coremark_v1.0# make ITERATIONS=10000

32-bit ARM systems

Coremark seems to have an issue when not running in a linux64 environment (e.g. 32-bit ARM). Add a flag to the make command: 

root@jph1:~/coremark_v1.0# make PORT_DIR=simple

Run benchmark (multi thread)

root@jph1:~/coremark_v1.0# make XCFLAGS="-DMULTITHREAD=8 -DUSE_PTHREAD"

Results

Coremark V1.0 results
CPU Freq Cores Coremark Coremark/MHz Coremark/Core Coremark/Core/MHz Parallel Execution Compile Flags
MIPS
Cavium Octeon II CN6645 2.50GHz 10 25671 10.268 2567 1.0268 10 Threads
Cavium Octeon II CN6645 2.50GHz 10 31172 12.468 3117 1.2468 10 Threads -O3 -funroll-all-loops --param max-inline-insns-auto=200
ARM
Calxeda Highbank (Cortex A9) 1.40GHz 4 11764 8.403 2941 2.1007 4 Threads
Calxeda Highbank (Cortex A9) 1.40GHz 4 12074 8.624 3018 2.1557 4 Threads -O3
Calxeda Midway (Cortex A15) 1.50GHz 4 20284 13.523 5071 3.3807 4 Threads
Calxeda Midway (Cortex A15) 1.50GHz 4 22013 14.675 5503 3.6687 4 Threads -O3
APM XGene1 (Cortex A57) 2.40GHz 8 49304 20.543 6163 2.5679 8 Threads
APM XGene1 (Cortex A57) 2.40GHz 8 54408 22.670 6801 2.8338 8 Threads -O3
Intel
Intel Atom C2550 2.4GHz 4 26044 10.852 6511 2.7129 4 Threads
Intel Atom C2550 2.4GHz 4 29333 12.222 7333 3.0554 4 Threads -O3
Intel Atom C2750 2.4GHz 8 50873 21.197 6359 2.6496 8 Threads
Intel Atom C2750 2.4GHz 8 58506 24.378 7313 3.0471 8 Threads -O3
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