Difference between revisions of "Labs:HPC rackmiddle"
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| − | + | ==Middle Rack== | |
| + | |||
<center> | <center> | ||
{| class="wikitable" cellpadding=5 style="border:1px; width:50%; background: white" | {| class="wikitable" cellpadding=5 style="border:1px; width:50%; background: white" | ||
! height="25pt" style="background: white" | || colspan="2" height="25pt"| Middle 42U Rack || Info: | ! height="25pt" style="background: white" | || colspan="2" height="25pt"| Middle 42U Rack || Info: | ||
|- | |- | ||
| − | ! | + | ! height="25pt" | 42 || colspan="2" | [[Ethernet Switch2 | Ethernet Switch]] |
|- | |- | ||
! height="25pt" | 41 || colspan="2" | Mellanox 10Gb Switch | ! height="25pt" | 41 || colspan="2" | Mellanox 10Gb Switch | ||
|- | |- | ||
| − | ! height="25pt" | 40 || colspan="2" | PXE | + | ! height="25pt" | 40 || colspan="2" | PXE SYS |
|- | |- | ||
| − | ! height="25pt" | 39 || colspan="2" | | + | ! height="25pt" | 39 || colspan="2" | [[ohpc2018 |New OHPC Headnode]] || style="background:White;" | OHPC/Boston head node 2018 |
|- | |- | ||
! height="25pt" | 38 || colspan="2" | Mellanox Switch | ! height="25pt" | 38 || colspan="2" | Mellanox Switch | ||
|- | |- | ||
| − | ! | + | ! height="25pt" | 37 || colspan="2" rowspan=2 style="background:Silver;" | [[QUAD_2_8| QUAD]] || rowspan=2 style="background:White;" | HPC |
| − | |- | + | |- |
! height="25pt" | 36 | ! height="25pt" | 36 | ||
|- | |- | ||
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! height="25pt" | 29 || colspan="2" style="background:White;"| | ! height="25pt" | 29 || colspan="2" style="background:White;"| | ||
|- | |- | ||
| − | ! height="25pt" | 28 || colspan="2" | [[GPU_2_1 |GPU]] || style="background:White;" | | + | ! height="25pt" | 28 || colspan="2" | [[GPU_2_1 |GPU]] || style="background:White;" | Connected to Mitaka Headnode for McLaren use |
|- | |- | ||
| − | ! height="25pt" | 27 || colspan="2" rowspan=2 style="background:Silver;" | [[QUAD_2_4| QUAD]] || rowspan=2 style="background:White;" | | + | ! height="25pt" | 27 || colspan="2" rowspan=2 style="background:Silver;" | [[QUAD_2_4| SkyLake QUAD]] || rowspan=2 style="background:White;" | Integrated with Mitaka Headnode (user: McLaren) |
|- | |- | ||
! height="25pt" | 26 | ! height="25pt" | 26 | ||
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! height="25pt" | 16 || colspan="2" style="background:White;"| | ! height="25pt" | 16 || colspan="2" style="background:White;"| | ||
|- | |- | ||
| − | ! height="25pt" | 15 || colspan="2" rowspan=2 style="background:Silver;" | [[QUAD_2_2| QUAD]] || rowspan=2 style="background:White;" | | + | ! height="25pt" | 15 || colspan="2" rowspan=2 style="background:Silver;" | [[QUAD_2_2| QUAD]] || rowspan=2 style="background:White;" | not in use |
|- | |- | ||
! height="25pt" | 14 | ! height="25pt" | 14 | ||
|- | |- | ||
| − | ! height="25pt" | 13 || colspan="2" rowspan=2 style="background:Silver;" | [[QUAD_2_1| QUAD]] || rowspan=2 style="background:White;" | | + | ! height="25pt" | 13 || colspan="2" rowspan=2 style="background:Silver;" | [[QUAD_2_1| QUAD]] || rowspan=2 style="background:White;" | not in use |
|- | |- | ||
! height="25pt" | 12 | ! height="25pt" | 12 | ||
Latest revision as of 09:33, 1 February 2018
Middle Rack
| Middle 42U Rack | Info: | ||
|---|---|---|---|
| 42 | Ethernet Switch | ||
| 41 | Mellanox 10Gb Switch | ||
| 40 | PXE SYS | ||
| 39 | New OHPC Headnode | OHPC/Boston head node 2018 | |
| 38 | Mellanox Switch | ||
| 37 | QUAD | HPC | |
| 36 | |||
| 35 | QUAD | HPC | |
| 34 | |||
| 33 | QUAD | HPC | |
| 32 | |||
| 31 | QUAD | HPC | |
| 30 | |||
| 29 | |||
| 28 | GPU | Connected to Mitaka Headnode for McLaren use | |
| 27 | SkyLake QUAD | Integrated with Mitaka Headnode (user: McLaren) | |
| 26 | |||
| 25 | |||
| 24 | |||
| 23 | QUAD | HPC | |
| 22 | |||
| 21 | |||
| 20 | |||
| 19 | |||
| 18 | |||
| 17 | |||
| 16 | |||
| 15 | QUAD | not in use | |
| 14 | |||
| 13 | QUAD | not in use | |
| 12 | |||
| 11 | |||
| 10 | |||
| 9 | |||
| 8 | |||
| 7 | |||
| 6 | |||
| 5 | |||
| 4 | |||
| 3 | |||
| 2 | |||
| 1 | |||