Difference between revisions of "Labs:HPC rackmiddle"
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| Line 35: | Line 35: | ||
! height="25pt" | 28 || colspan="2" | [[GPU_2_1 |GPU]] || style="background:White;" | Connected to Mitaka Headnode for McLaren use | ! height="25pt" | 28 || colspan="2" | [[GPU_2_1 |GPU]] || style="background:White;" | Connected to Mitaka Headnode for McLaren use | ||
|- | |- | ||
| − | ! height="25pt" | 27 || colspan="2" rowspan=2 style="background:Silver;" | [[QUAD_2_4| QUAD]] || rowspan=2 style="background:White;" | | + | ! height="25pt" | 27 || colspan="2" rowspan=2 style="background:Silver;" | [[QUAD_2_4| SkyLake QUAD]] || rowspan=2 style="background:White;" | Integrated with Mitaka Headnode (user: McLaren) |
|- | |- | ||
! height="25pt" | 26 | ! height="25pt" | 26 | ||
Revision as of 10:13, 25 April 2017
Middle Rack
| Middle 42U Rack | Info: | ||
|---|---|---|---|
| 42 | Ethernet Switch | ||
| 41 | Mellanox 10Gb Switch | ||
| 40 | PXE | ||
| 39 | PXE | ||
| 38 | Mellanox Switch | ||
| 37 | QUAD | HPC | |
| 36 | |||
| 35 | QUAD | HPC | |
| 34 | |||
| 33 | QUAD | HPC | |
| 32 | |||
| 31 | QUAD | HPC | |
| 30 | |||
| 29 | |||
| 28 | GPU | Connected to Mitaka Headnode for McLaren use | |
| 27 | SkyLake QUAD | Integrated with Mitaka Headnode (user: McLaren) | |
| 26 | |||
| 25 | |||
| 24 | |||
| 23 | QUAD | HPC | |
| 22 | |||
| 21 | |||
| 20 | |||
| 19 | |||
| 18 | |||
| 17 | |||
| 16 | |||
| 15 | QUAD | not in use | |
| 14 | |||
| 13 | QUAD | not in use | |
| 12 | |||
| 11 | |||
| 10 | |||
| 9 | |||
| 8 | |||
| 7 | |||
| 6 | |||
| 5 | |||
| 4 | |||
| 3 | |||
| 2 | |||
| 1 | |||